1. Field of the Invention
The present invention relates to a type of a MOSFET device called lateral DMOS FET device.
2. Description of the Background Art
There are two types of a conventional power DMOSFET device, including a vertical DMOSFET (VDMOS) which has a drain electrode on a back side of a substrate, and a lateral DMOSFET (LDMOS) which has a drain electrode formed on a top side of a substrate.
Now, an example of a conventional n-channel type VDMOS shown in FIG. 1 will be described.
In this n-channel type VDMOS, an n.sup.+ -type diffusion layer 4 is formed inside a p-type diffusion layer 3, which is formed inside an n-type epitaxial layer 2 formed on an n.sup.+ -type silicon substrate 12. Also, on a top side of the n-type epitaxial layer 2, a gate electrode 7 is formed on a gate insulation film 6 formed over the p-type diffusion layer 3 functioning as a channel region and the n.sup.+ -type diffusion layer 4 functioning as a source region. The gate electrode 7 is covered by an interlayer insulation film 8, over which a source electrode 16 is formed. In addition, on a back side of the n.sup.+ -type silicon substrate 12 which functions as a drain region, there is formed a drain electrode 13.
In such a VDMOS, the source electrode 16 and the drain electrode 13, which are main passages for the current, are separately provided on the top and back sides of the substrate 12, so that there is no need to collect the current planewise. As a result, the resistance and the area loss due to these components are reduced such that there has been an advantage that the on resistance can be lowered considerably.
However, such a VDMOS has been associated with the following problems.
First, because the drain region is formed by the n.sup.+ -type silicon substrate 12, it has been difficult to form a plurality of VDMOSs on a single substrate, and operating each of them independently, or to form a VDMOS along with other devices such as a CMOS or a bipolar IC.
Secondly, the on resistance is parasitically introduced into the substrate resistance in such a VDMOS.
It has recently become popular in the VDMOS to reduce the on resistance by using finer p-type diffusion layer 3 and n.sup.+ -type diffusion layer 4 manufactured by the improved fine manufacturing technique. There is a device of less than 100 V voltage capacity, which has the on resistance of less than 1 m.OMEGA..multidot.cm.sup.2. Such a device is disclosed by Krishina Shenai et al. in "Blanket LPCVD tungusten Silicide technology for Smart Power Applications", IEEE EDL Vol. 10, No. 5, June 1989.
However, when the finer manufacturing is used, although the channel resistance can be reduced, the resistance of the substrate which makes up the majority of the chip thickness becomes unignorable. Namely, the on resistance R.sub.on can be expressed in terms of the channel resistance R.sub.ch, accumulation resistance R.sub.ac, epitaxial layer spreading resistance R.sub.epi, and substrate resistance R.sub.sub as: EQU R.sub.on =R.sub.ch +R.sub.ac +R.sub.epi +R.sub.sub ( 1)
This implies that the substrate resistance R.sub.sub becomes 30-40% of the entire on resistance R.sub.on for a cell size of 10.times.10 .mu.m, using a gate oxide film thickness=500 .ANG., a gate effective voltage=15 V, an epitaxial layer specific resistance=0.4 .OMEGA..multidot.cm, an epitaxial layer thickness=6.5 .mu.m, a substrate specific resistance=0.04 .OMEGA..multidot.cm, and a substrate thickness=380 .mu.m.
The substrate resistance can be reduced by increasing the impurity density or by thinning the substrate thickness, but the former has a problem that the deterioration of the crystallization property of the epitaxial layer can also be caused, while the latter has a problem of a wafer cracking due to the reduced mechanical strength. Thus, there is a limit to an extent that the on resistance can be reduced.
On the other hand, an example of one type of a conventional n-channel type LDMOS is shown in FIG. 2, which will now be described.
In this n-channel type LDMOS, an n.sup.+ -type diffusion layer 4 is formed inside a p-type diffusion layer 3, which is formed inside an n-type epitaxial layer 2 formed on a p-type silicon substrate 1. Also, on a top side of the n-type epitaxial layer 2, a gate electrode 7 is formed on a gate insulation film 6 formed over the p-type diffusion layer 3 functioning as a channel region and the n.sup.+ -type diffusion layer 4 functioning as a source region. The gate electrode 7 is covered by an interlayer insulation film 8, over which a source electrode 16 is formed. In addition, there is provided an n-type diffusion layer 15 which is making a contact with an n.sup.+ -type buried layer 14 formed between the p-type silicon substrate 1 and the n-type epitaxial layer 2, and an n.sup.+ -type diffusion layer 5 is formed inside the n-type diffusion layer 15, such that a drain electrode 17 can be formed over the n.sup.+ -type diffusion layer 5 on a top side of the p-type silicon substrate 1.
In such an LDMOS, because it is entirely formed on the grounded p-type silicon layer 1, there has been advantages that such an LDMOS can be formed along with the other electrically isolated devices or LDMOSs, and the effect of the substrate resistance on the on resistance is very small.
However, there has also been a problem that the device area have to be enlarged in order to incorporate the n-type diffusion layer 15 and the drain electrode 17. The area required for this reason needs to be as large as that covered by the source electrode, in order to have the drain current flow.
In this type of LDMOS, the source electrode 16 and the drain electrode 17 are arranged as shown in FIG. 3. As shown, the source electrode 16 and the drain electrode 17 are shaped in comblike shapes and are arranged to be gearing with each other, in contrast to the case of VDMOS in which these components are formed over the entire front and back sides. These source and drain electrodes 16 and 17 are also shaped such that their width becomes wider toward positions of bonding pads 18 and 19. The width in a vicinity of the bonding pads 18 and 19 have to be greater for the device of larger current capacity, and therefore the dead space in the device increases as its current capacity increases.
Now, the reduction of the on resistance by using the improved fine manufacturing technique, popularly exercised for a VDMOS as already mentioned above, is not effective in reducing the dead space in the LDMOS, so that the extent by which the on resistance can be reduced has been rather limited in the LDMOS.
Also, in this type of LDMOS, there has been a problem that although the substrate resistance is very small, the parasitic drain resistance due to the resistance of n-type diffused layer and n.sup.+ -type buried layer is large. This parasitic drain resistance can be reduced effectively by enlarging the total area of the n-type diffusion layer 15 so as to reduce the distance that the current have to travel through the n.sup.+ -type buried layer 14. However, this in turn increases the dead space in the LDMOS.
Thus, the on resistance in this type of the LDMOS has usually been over twice as large as the VDMOS of the same device area. For this reason, the use of this type of the LDMOS has been limited to cases involving a small or medium amount of current only. For a case involving a large amount of current such as that over 10A, the device area of the LDMOS becomes practically too large.
There is also another type of an LDMOS in which the current flows along the substrate surface, which is shown in FIG. 4 and will now be described.
In this LDMOS of FIG. 4, a p-type diffusion layer 3 functioning as a channel region and an n.sup.+ -type diffusion layer 5 functioning as a drain contact region are formed inside an n-type epitaxial layer 2 formed on a p-type silicon substrate 1. Inside the p-type diffusion layer 3, n.sup.+ -type diffusion layer 4 functioning as a source region is formed. Also, on a top side of the p-type silicon substrate 1, a gate electrode 7 is formed on a gate insulation film 6 formed over the p-type diffusion layer 3 and the n.sup.+ -type diffusion layer 4. The gate electrode 7 is covered by an interlayer insulation film 8, over which a source electrode 16 is formed. In addition, over the n.sup.+ -type diffusion layer 5, a drain electrode 17 is formed on a top side of the p-type silicon substrate 1.
In such an LDMOS, just as in the LDMOS of FIG. 2 described above, because it is entirely formed on the grounded p-type silicon layer 1, there is an advantage that such an LDMOS can be formed along with the other electrically isolated devices or LDMOSs.
Furthermore, in this type of the LDMOS, the parasitic drain resistance can be reduced as there is no n.sup.+ -type buried layer 14 through which the current have to pass.
However, this type of the LDMOS is also associated with the problem of the enlargement of the device size due to the inclusion of the n.sup.+ -type diffusion layer 5 and the drain electrode 17, which gives rise to the problem of the larger dead space for the larger current capacity, as in the LDMOS of FIG. 2.
In addition, because the source electrode 16 and the drain electrode 17 are in comblike shapes and also because the source region 4 and the drain connector region 5 have to be arranged adjacent to each other, the source region 4 have to be in stripe-shape which runs parallel to the comblike shape of the source electrode 16, such that the cell arrangement commonly utilized in the VDMOS has not been applicable to the LDMOS. The stripe arrangement is known to have the smaller channel width per unit area, so that there is a limit to which the on resistance can be reduced in the stripe arrangement, compared with the cell arrangement.
Thus, the on resistance in this type of the LDMOS has also usually been over twice as large as the VDMOS of the same device area.
Therefore, two types of the conventional LDMOS described so far are known to be advantageous in that they are suitable for being integrated with the other devices or made into multiple output configuration, as it has the drain electrode on the top side of the substrate, but they also have the problem of having the higher on resistance compared with the VDMOS which has the drain electrode on the back side of the substrate, such that they are less desirable in terms of costs, as well as in terms of the limit on the current capacity.
Also, in the LDMOS, since the current flows mostly on the top side of substrate, the effect of the substrate resistance becomes small. However, the device area have to be enlarged in order to incorporate the n-type diffusion layer 15 and the drain electrode 17, and the resulting increase of the wirings reduces the cell density.
As an effective cell pattern for LDMOS which can resolve the problems of the conventional LDMOS described above, a mesh-gate structure shown in FIG. 5 has been known conventionally.
In this mesh-gate structure, source openings 105 and drain openings 106 are formed by square cuttings on the gate electrode 107, and are arranged one next to another. The drain and source electrodes 113A and 116A are arranged over the source and drain openings 105 and 106 in a stripe pattern running obliquely.
On the source openings 105, the p-type channel region 103 and the n-type source region 104 are formed by using the diffusion self-align technique. On the drain openings 106, high density n-type impurities are doped in order to obtain the low Ohmic contact with the electrode.
In this mesh-gate structure, the on resistance can be reduced efficiently as the source and drain are separated in each unit cell. However, since the source openings 105 and the drain openings 106 have the same area, there is a problem in reducing the on resistance further.
Namely, the on resistance R.sub.on in this case can be expressed in terms of the channel resistance R.sub.ch, accumulation resistance R.sub.ac, epitaxial layer spreading resistance R.sub.epi, and substrate resistance R.sub.sub as: ##EQU1## where the first term on the right hand side of the equation (2) R.sub.ch, largely depends on the size of the source openings 105, while the second term on the right hand side largely depends on the size of the drain openings 106.
However, since the source openings 105 and the drain openings 106 have the same area, these first and second terms on the right hand side are automatically determined when the resistance of each part is determined from other conditions on the device such as the voltage capacity.
In particular, when the values of the first term and the second term are largely different, the larger one makes a dominant contribution to the on resistance, and sets the limit to an extent by which the on resistance can be reduced.